Block
A concurrent statement used to group together concurrent statements, and make local declarations. Guarded blocks provide an alternative (but little used) way to write Register Transfer Level descriptions. The execution of guarded signal assignments within the block is controlled by the guard expression at the top.
Syntax
BlockLabel: block [(GuardExpression)] [is]
[Generic;
[GenericMap;]]
[Port;
[PortMap;]]
Declarations...
begin
ConcurrentStatements...
end block [BlockLabel];
Placement
PACKAGE Pack IS
...
END PACKAGE Pack;
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PACKAGE BODY Pack IS
...
END PACKAGE BODY Pack;
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Blk:BLOCK
...
BEGIN
... 
END BLOCK Blk;
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ENTITY Ent IS
...
BEGIN
...
END ENTITY Ent;
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ARCHITECTURE Arc OF Ent IS
...
BEGIN
...
END ARCHITECTURE Arc;
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CONFIGURATION Conf OF Ent IS
...
END CONFIGURATION Conf;
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Proc:PROCESS(...)
...
BEGIN
...
END PROCESS Proc;
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PROCEDURE P(...) IS
...
BEGIN
...
END PROCEDURE P;
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FUNCTION F(...) RETURN Tp IS
...
BEGIN
...
END FUNCTION F;
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Gen:GENERATE(...)
...
BEGIN
...
END GENERATE Gen;
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|
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Things to remember
Some commercial synthesis tools do not support blocks.
Tips
It is not necessary to learn and use blocks and related syntax such as guarded signal assignments. It is generally more efficient for simulation to use processes instead.
Example
signal P, Q, R: STD_LOGIC;
...
Logic: block
port (A, B: in STD_LOGIC;
F : out STD_LOGIC);
port map (A => P, B => Q, F => R);
begin
F <= A nand B;
end block Logic;
Sync: block (Rising_edge(Clock))
begin
Q <= guarded D; -- This assignment occurs on the clock edge
QB <= not Q; -- This assignment occurs when Q changes
end block Sync;
See Also
Signal Assignment, Concurrent Statement, Disconnect
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